1. Field of the Invention
The present invention relates to a semiconductor device including a multilayer interconnect structure, and to a method of manufacturing the same.
2. Description of the Related Art
These years, in the field of semiconductor devices provided with a memory circuit, a logic circuit and the like, an impact of a signal delay to the circuit performance, as well as degradation in reliability of an interconnect due to stress migration (SM) and electromigration (EM) have been focused as a critical issue to be addressed.
A signal delay is considered to take place because of the following two factors. One of the factors is an electrical resistance existing in a long-range interconnect for transmitting a clock signal. For minimizing this problem it is necessary to reduce the electrical resistance of the interconnect, which may be achieved by increasing a thickness of the interconnect, or employing a material having a smaller electrical resistance to constitute the interconnect, for example. The other factor is a parasitic capacitance in a short-range interconnect of a highly integrated pattern such as a memory cell. It is between adjacent interconnects that a parasitic capacitance resultant from micronization of a pattern typically emerges. Such being the case, reducing a parasitic capacitance among interconnects provided in a same layer is effective in minimizing a signal delay caused by the parasitic capacitance.
Based on the foregoing, for a long-range interconnect it is effective to increase a thickness of the interconnect to thereby reduce an electrical resistance of the interconnect, and for a short-range interconnect it is effective to reduce a thickness of the interconnect, to thereby reduce a parasitic capacitance.
Following is a review of an interconnect structure in a conventional semiconductor device. The example described below represents a case where a conductive layer constituting the interconnect is predominantly composed of copper (Cu), which has a lower electrical resistance than aluminum (Al).
FIG. 8 is a schematic cross-sectional view showing a conventional interconnect structure.
As shown in FIG. 8, an underlying silicon oxide layer 2 is provided on a semiconductor substrate 1. A plurality of interconnects is disposed in an interlayer dielectric layer on the underlying silicon oxide layer 2. And the interconnects are mutually connected via a first via plug 52, a second via plug 54, a third via plug 56, a fourth via plug 58, and a fifth via plug 60. A first interconnect 4, a second interconnect 6 and a third interconnect 8 correspond to the short-range interconnect, while a fourth interconnect 10, a fifth interconnect 12 and a sixth interconnect 14 correspond to the long-range interconnect. Here, the long-range interconnect, the short-range interconnect and a via plug are constituted of a pure Cu layer.
Also, as already stated, the long-range interconnects are formed in a greater thickness so as to reduce an electrical resistance existing therein, while the short-range interconnects are made thinner so as to reduce a parasitic capacitance. Accordingly, the long-range interconnects are thicker than the short-range interconnects. Hereinafter, an interconnect having a greater thickness as the long-range interconnect will be referred to as a deep trench interconnect, and an interconnect having a reduced thickness as the short-range interconnect will be referred to as a shallow trench interconnect.
Meanwhile, referring to the degradation in reliability, a known effective countermeasure is employing a Cu alloy layer, which is a Cu layer to which an impurity such as magnesium (Mg), Al, or silicon (Si) has been added, as a material of an interconnect. As a result of employing a Cu alloy layer to constitute an interconnect, the added impurity is deposited at a grain boundary of copper in the interconnect, which increases resistance against the EM caused by an increase in current density.
Now, a multilayer interconnect structure including interconnects to which an impurity has been added will be described.
FIG. 9 is a schematic cross-sectional view showing a multilayer interconnect structure.
As shown in FIG. 9, a first interconnect 20, a second interconnect 22 and a third interconnect 24, which are the short-range interconnects, are made thinner as in FIG. 8, to reduce a parasitic capacitance. Further, these short-range interconnects are constituted of a Cu alloy layer including one selected out of silver, palladium, platinum, tin (Sn), chrome, zirconium and titan, added by CVD (Chemical Vapor Deposition), for preventing the degradation in EM resistance incurred by reducing a thickness of the interconnect (Ref. JP-A Laid Open No. H09-289214). In addition, a fourth interconnect 10, a fifth interconnect 12 and a sixth interconnect 14, which are the long-range interconnects, are constituted of a pure Cu layer, as well as in a greater thickness as in FIG. 8, to reduce an interconnect resistance.
However, in the case of employing a pure Cu layer for constituting the long-range interconnects and the short-range interconnects, when the short-range interconnect is formed in a reduced thickness, a wide interconnect, which has a relatively large width among the short-range interconnects, is also formed in a reduced thickness. A reduced thickness of the interconnect leads to a decrease in free energy in the interconnect bulk. On the other hand, a larger width of an interconnect allows emergence of more free energy on a surface of the interconnect, because of an increase in area of the interconnect pattern. Therefore, as shown in FIG. 10A, in the case where a thickness of a wide interconnect 192 formed in the silicon oxide layer 103 is, for instance, less than 200 nm, the free energy on the interconnect surface becomes greater than that in the interconnect bulk, owing to which an aggregation reaction is prone to be caused by a heat treatment in a subsequent manufacturing process. The aggregation reaction often results in a disconnection in the interconnect, thereby disabling the interconnect. In the case of a narrow interconnect 194, since the free energy on a surface thereof is minor, the aggregation reaction is not likely to take place. Meanwhile, in FIGS. 10A and 10B, the interconnect is provided thereon with a cap layer 196, to serve as a Cu diffusion barrier.
Now referring to SM resistance, at least either of thermal stress because of repeated heat treatments in a manufacturing process (hereinafter referred to as “high-temperature short-term=HTST stress”), or thermal stress imposed by an operational heat during a use of the semiconductor device (hereinafter referred to as “low-temperature long-term=LTLT stress”) is prone to incur degradation in the SM resistance. To minimize this problem, it is effective to employ the Cu alloy layer for constituting the interconnect because, as shown in FIG. 10B, an impurity oxide layer 198 is formed on a surface of the interconnect during a cleaning process, following a CMP (Chemical and Mechanical Polishing) process performed to remove an excessive interconnect material on an upper surface of the silicon oxide layer 103, so that the impurity oxide layer 198 covers a surface of the interconnect, to thereby restrain the aggregation reaction that may be caused by a heat treatment.
Also, with a further micronization of the pattern, a grain structure of a narrow interconnect, which is relatively narrower than a wide interconnect, turns to a bamboo structure. In addition, in the case where a barrier metal is provided on a bottom portion and a side wall of the interconnect, a ratio of the barrier metal amount becomes relatively higher with respect to the Cu amount. Accordingly, the problem of the EM can be eliminated. However, adding an impurity to the narrow interconnect often results in causing a signal delay, since a specific resistance of the interconnect is increased. Consequently, it should be concluded that employing a Cu alloy layer having a high concentration of impurity for forming the narrow interconnect is not propriety.
On the other hand, in case of employing a pure Cu layer for forming an interconnect, at least either of the HTST stress or the LTLT stress causes a defect in a grain boundary of the interconnect to move to a junction between the interconnect and a via plug, thereby allowing emergence of a void induced by the stress (hereinafter referred to as a “Stress Induced Void=SIV) at the junction. Since a wide interconnect includes a more number of grain boundaries than a narrow interconnect does, the SIV at the junction grows larger. In case where the junction has a sufficiently large area, an electrical continuity between the wide interconnect and the via plug may still be maintained. However, when the area of the junction is made smaller in compliance with the micronization, it is most probable that an SIV that has grown at the junction causes an open defect, which electrically disconnects the wide interconnect from the via plug.